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W631GG6KB
1. GENERAL DESCRIPTION
The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words ? 8 banks ? 16 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -15, 15I,
15A and 15K. The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12,
12I, 12A and 12K speed grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I
industrial grade which is guaranteed to support -40°C ≤ T CASE ≤ 95°C). The -15, 15I, 15A and 15K
speed grades are compliant to the DDR3-1333 (9-9-9) specification (the 15I industrial grade which is
guaranteed to support -40°C ≤ T CASE ≤ 95°C).
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (T A ) surrounding the device cannot be less than -40°C or greater than +95°C (for 12A
and 15A), +105°C (for 12K and 15K), and the case temperature (T CASE ) cannot be less than -40°C or
greater than +95°C (for 12A and 15A), +105°C (for 12K and 15K). JEDEC specifications require the
refresh rate to double when T CASE exceeds +85°C; this also requires use of the high-temperature self
refresh option. Additionally, ODT resistance and the input/output impedance must be derated when
T CASE is < 0°C or > +85°C.
The W631GG6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
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Power Supply: V DD , V DDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Publication Release Date: Dec. 09, 2013
Revision A05
-5-
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